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During the 23rd Synopsys EDA Interoperability Forum an update was given on the status of the IPLnow efforts (http://www.iplnow.com). The majority of the new work in iPDK has to do with Analog Constraints. Here are some of my thoughts concerning analog constraints: Constraints are a type of meta data that describe behavior expected in a [...] On Thursday Oct. 21 Synopsys held their 23rd EDA Interoperability Forum. The following are some of my observations about the presentations. ARM It was hinted at by a representative from ARM that they actively are modifying their processors to improve the performance of Adobe Flash playback. Would Intel or some other processor vendor change their [...] I gave a presentation last year at the MOS-AK workshop in San Francisco. The people attending this workshop are all interested in simulation models for semiconductors. One of the comments made during the workshop, was that circuit designers blame the models when their circuits do not work right. In most cases what is meant as [...] As feature size is reduced in chip design life for digital design gets way more complicated. We are building 45 and 32nm chips using 193nm light sources. This is like using a 4 inch wide brush to paint 1 inch lines, something doable, but inherently limiting. Double patterning is beginning to be used to achieve [...] I attended DVCon today at the Double Tree Hotel in San Jose. Went to the keynote address by Aart de Geus of Synopsys, and the panel session “EDA: Dead or Alive?” The Panel session was hosted by Peggy Aycinena of EDA Confidential. Also in attendance were Gabe Moretti or Gabe on EDA, and Gary Smith [...] |
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