Notes from Silicon Valley

I gave a presentation last year at the MOS-AK workshop in San Francisco. The people attending this workshop are all interested in simulation models for semiconductors. One of the comments made during the workshop, was that circuit designers blame the models when their circuits do not work right. In most cases what is meant as model, [...]

As feature size is reduced in chip design life for digital design gets way more complicated. We are building 45 and 32nm chips using 193nm light sources. This is like using a 4 inch wide brush to paint 1 inch lines, something doable, but inherently limiting. Double patterning is beginning to be used to achieve the [...]

I attended DVCon today at the Double Tree Hotel in San Jose. Went to the keynote address by Aart de Geus of Synopsys, and the panel session “EDA: Dead or Alive?”

The Panel session was hosted by Peggy Aycinena of EDA Confidential. Also in attendance were Gabe Moretti or Gabe on EDA, and Gary Smith of Gary [...]

Comments about TSMC’s 2004 Technology Forum – Moore’s law is not broken, its just slowed down. Not a true statement, just wishful thinking. There seems to be a fear that if we declare Moore’s law is over, that the whole semiconductor business is over.

There are still only 40 products in development in 90nm, about twice as [...]