As feature size is reduced in chip design life for digital design gets way more complicated. We are building 45 and 32nm chips using 193nm light sources. This is like using a 4 inch wide brush to paint 1 inch lines, something doable, but inherently limiting. Double patterning is beginning to be used to achieve the small feature sizes, by using two large feature masks, and printing each separately, the intention is to create the smaller feature size through two large steps[1]. By having two patterning steps, there are two alignment steps. This means that there will be misalignment, and this will be part of the inherent variation of the transistor. While this may be ok for digital design, is analog design going to be feasible? My feeling is this will make analog design so hard, so low performance, that it will force the push to using deep UV, from 193nm.
[1] – http://en.wikipedia.org/wiki/Double_patterning